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Microcomputer Components
8-Bit CMOS Microcontroller
C511/C511A C513/C513A C513A-H
Data Sheet 06.96
Data Sheet C511/C511A/C513/C513A/C513A-H Revision History : Current Version : 06.96 Previous Releases : Page Several 41 02.96, 05.95 Subjects (changes since last revision) Corrections of text Figure 22: external clock configuration corrected
8-Bit CMOS Microcontroller Family
C511 C511A C513 C513A C513A-H
Preliminary
q q q q q q q q q q q q q
Fully software compatible to standard 8051/8052 microcontrollers Up to 12 MHz operating frequency Up to 12 Kx8 ROM / EEPROM Up to 256x8 RAM Up to 256 x 8 XRAM Four 8-bit ports Up to three 16-bit Timers / Counters (Timer 2 with Up/Down and 16-bit Autoreload Feature) Synchronous Serial Channel (SSC) Optional USART Up to seven interrupt sources, two priority levels Power Saving Modes P-LCC-44 package (C513A also in P-MQFP-44 package) TA : 0 C to 70 C Temperature Ranges : SAB-C511 / 511A / 513 / 513A / C513A-H TA : -40 C to 85 C SAF-C513A
Semiconductor Group
3
06.96
C511 / C513
The C511, C511A, C513, C513A, and C513A-H are members of a family of low cost microcontrollers, which are software compatible with the components of the SAB 8051, SAB 80C51 and C500 families. The first four versions contains a non-volatile read-only (ROM) program memory. The C513A-H is a version with a 12 Kbyte EEPROM instead of ROM. This device can be used for prototype designs which have a demand for reprogrammable on-chip code memory. The members of the microcontroller family differ in functionality according table 1. They offer different ROM sizes, different RAM/XRAM sizes and a different timer/USART configuration. Common to all devices is an advanced SSC serial port, a second synchronous serial interface, which is compatible to the SPI serial bus industry standard. The functionality of the C513A-H is a superset of all ROM versions of the C511/C513 family. Table 1 Functionality of the C511/C513 MCUs Device C511 C511A C513 C513A C513A-H
1)
ROM Size 2.5 KB 4 KB 8 KB 12, 16 KB -
EEPROM Size - - - - 12 KB
RAM Size 128 B 256 B 256 B 256 B 256 B
XRAM Size - - - 256 B 256 B
Timers 1) T0, T1 T0, T1 T0, T1, T2 T0, T1, T2 T0, T1, T2
USART - -
SSC
T0/T1 refers to the standard 8051 timer 0/1 units, T2 refers to the 8052 timer 2 unit.
Figure 1 C511/513 Logic Symbol
Semiconductor Group
4
C511 / C513
Table 2 Ordering Information Type C511-RN C511A-RN C513-1RN C513A-RN Ordering Code Package Description (8-Bit CMOS microcontroller) with mask-programmable ROM (2.5K), 12 MHz with mask-programmable ROM (4K), 12 MHz with mask-programmable ROM (8K), 12 MHz with mask-programmable ROM (12K), 12 MHz with mask-programmable ROM (12K), 12 MHz, ext. temp. - 40 C to 85 C with mask-programmable ROM (16K), 12 MHz with mask-programmable ROM (16K), 12 MHz, ext. temp. - 40 C to 85 C
Q67120-DXXXX P-LCC-44 Q67120-DXXXX P-LCC-44 Q67120-DXXXX P-LCC-44 Q67120-DXXXX P-LCC-44 Q67120-DXXXX P-LCC-44
C513A-2RN
Q67120-DXXXX P-LCC-44 Q67120-DXXXX P-LCC-44
C513A-2RM
Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (16K), 12 MHz Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (16K), 12 MHz, ext. temp. - 40 C to 85 C
C513A-LN
Q67120-C1017 Q67120-C1035
P-LCC-44 P-LCC-44
for external memory (12 MHz) for external memory (12 MHz), ext. temp. - 40 C to 85 C
C513A-LM
Q67120-C1026 Q67120-C1036
P-MQFP-44 for external memory (12 MHz) P-MQFP-44 for external memory (12 MHz), ext. temp. - 40 C to 85 C P-LCC-44 with reprogrammable EEPROM (12K), 12 MHz, ext. temp. - 40 C to 85 C
C513A-HN
Q67120-C0989
Note : The ordering number of the ROM types (DXXXX extension) is defined after program release (verification) of the customer.
Semiconductor Group
5
C511 / C513
Figure 2 P-LCC-44 Package Pin Configuration (Top View) If the C513A-H is used in programming mode, the pin configuration is different to figure 2 and 3 (see figure 5).
Semiconductor Group
6
C511 / C513
Figure 3 P-MQFP-44 Package Pin Configuration of the C513A (Top View)
Semiconductor Group
7
C511 / C513
Table 3 Pin Definitions and Functions Symbol Pin Number P-LCC- P-MQFP44 44 P1.7-P1.0 9-2 3-1, 44-40 I/O Port 1 is a bidirectional I/O port with internal pull-up resistors. Port 1 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 1 also contains the timer 2 and SSC pins as secondary function. In general the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. For the outputs of the SSC (SCLK, STO) special circuitry is implemented, providing true push-pull capability. The STO output in addition will have true tristate capability. When used for SSC inputs, the pull-up resistors will be switched off and the inputs will float (high ohmic inputs). The alternate functions are assigned to port 1, as follows: 2 3 4 5 6 7 40 41 42 43 44 1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 T2 T2EX SCLK SRI STO SLS Input to counter 2 1) Capture -Reload trigger of timer 2 Up-Down count SSC Master Clock Output SSC Slave Clock Input SSC Receive Input SSC Transmit Output Slave Select Input I/O*) Function
1)
1) not available in the C511/511A
*) I = Input O = Output
Semiconductor Group
8
C511 / C513
Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC- P-MQFP44 44 P3.0-P3.7 11, 13-19 5, 7-13 I/O Port 3 is a bidirectional I/O port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3 as follows: 11 5 P3.0 RXD Receiver data input (asynchronous) or data input/output (synchronous) of serial interface (USART) 1) Transmitter data output (USART) 1) (asynchronous) or clock output (synchronous) of serial interface Interrupt 0 input / timer 0 gate control Interrupt 1 input / timer 1 gate control Counter 0 input Counter 1 input Write control signal : latches the data byte from port 0 into the external data memory Read control signal : enables the external data memory to port 0 I/O*) Function
13
7
P3.1
TXD
14 15 16 17 18
8 9 10 11 12
P3.2 P3.3 P3.4 P3.5 P3.6
INT0 INT1 T0 T1 WR
19
13
P3.7
RD
1)
not available in the C511/511A
XTAL2
20
14
-
XTAL2 Output of the inverting oscillator amplifier.
*) I = Input O = Output
Semiconductor Group
9
C511 / C513
Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC- P-MQFP44 44 XTAL1 21 15 - XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. Port 2 is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal program execution. RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal resistor to VSS permits power-on reset using only an external capacitor to VCC. I/O*) Function
P2.0-P2.7
24-31
18-25
I/O
PSEN
32
26
O
RESET
10
4
I
*) I = Input O = Output
Semiconductor Group
10
C511 / C513
Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number P-LCC- P-MQFP44 44 ALE 33 27 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periodes except during an external data memory access. If no external memory is used, the ALE signal generation can be inhibited, reducing system RFI, by clearing register bit EALE in the SYSCON register. External Access Enable When held at high level, instructions are fetched from the internal ROM when the PC is less than the size of the internal ROM : C511 0A00H C511A 1000H C513 2000H C513A/A-H 3000H C513A-2R 4000H When held at low level, the microcontroller fetches all instructions from external program memory. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1s. External pullup resistors are required during program verification. Circuit ground potential Power Supply terminal for all operating modes No connection, do not connect externally I/O*) Function
EA
35
29
I
P0.0-P0.7
43-36
37-30
I/O
VSS VCC
N.C.
22 44 1, 12, 23, 34
16 38 6, 17, 28, 39
- - -
*) I = Input O = Output
Semiconductor Group
11
C511 / C513
Figure 4 C513A-H Logic Symbol in Programming Mode
Figure 5 C513A-H Pin Configuration in Programming Mode (P-LCC-44)
Semiconductor Group
12
C511 / C513
Table 4 Pin Definitions and Functions in Programming Mode (C513A-H only) Symbol PRES Pin Number P-LCC-44 15 I Programming Interface Reset A high level on this input resets the programming interface and its registers to their initial state. Bidirectional Address/Data Bus AD0-7 is used to transfer data to and from the registers of the programming interface and to read the data of the memory field during EEPROM verification. Programming Address Latch Enable This input is used to latch address information at AD0-7. The trailing edge of PALE is used to latch the register addresses. Each read or write access in programming mode must be initiated by a PALE high pulse. Programming Read Control A low level at this pin (and PCS=low) enables the AD0-7 buffers for reading of the data or control registers of the programming interface. Programming Write Control A low level at this pin (and PCS=low) causes the data at AD07 to be written into the data or control registers of the programming interface. Programming Chip Select A low level at this pin enables the access to the registers of the programming interface. If PCS is active, either PRD or PWR control whether data is read or written into the registers. PCS should be always deactivated between subsequent accesses to the programming interface. XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. During the device programming a clock must be always supplied. I/O*) Function
AD0 - AD7 43 - 36
I/O
PALE
16
I
PRD
18
I
PWR
19
I
PCS
17
I
XTAL2 XTAL1
20 21
- -
*) I = Input O = Output
Semiconductor Group
13
C511 / C513
Table 4 Pin Definitions and Functions in Programming Mode (C513A-H only) (cont'd) Symbol PMS0 PMS1 PMS2 PMS3 Pin Number P-LCC-44 35 33 32 10 I Programming Mode Select PMS0-3 are used to put the C513A-H into the program-ming mode. In normal mode the programming mode select pins have the meaning as shown in the table below. PMS0-3 must be set to the logic level as described in the table below. Normal Mode Pin Names EA ALE PSEN RESET Progr. Mode Pin Names PMS0 PMS1 PMS2 PMS3 Required Logic Level 0 1 0 1 I/O*) Function
VSS VCC
N.C.
22 44 1-9, 11-14, 23-31, 34
- - -
Circuit ground potential Power supply terminal for all operating modes No connection These pins must not be connected.
*) I = Input O = Output
Semiconductor Group
14
C511 / C513
Functional Description The C511/C513 microcontrollers are fully compatible to the standard 8051/80C52 and C500 microcontroller family. While maintaining all architectural and operational characteristics of the 80C52/C500 the C511/C513 incorporates enhancements such as additional internal XRAM and a second (synchronous) serial interface unit. Figure 6 shows a block diagram of the C511/C513 microcontroller family.
Figure 6 Block Diagram of the C511/C513 Units
Semiconductor Group
15
C511 / C513
CPU The C511/C513 are efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and for bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % threebyte instructions. With a 12 MHz crystal, 58 % of the instructions execute in 1 s.
Special Function Register PSW (Address D0H) MSB 7 CY
Reset Value : 00H LSB 0 P PSW
Bit No. D0H
6 AC
5 F0
4 RS1
3 RS0
2 OV
1 F1
Bit CY AC F0 RS1 RS0 0 0 0 1 1 0 1 1 OV F1 P
Function Carry Flag Auxiliary Carry Flag (for BCD operations) General Purpose Flag Register Bank select control bits Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH Overflow Flag General Purpose Flag Parity Flag Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
Semiconductor Group
16
C511 / C513
Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area. The 34 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in table 5 and table 6. In table 5 they are organized in groups which refer to the functional blocks of the C511/C513. Table 6 illustrates the contents of the SFRs, e.g. the bits of the SFRs, in numeric order of their addresses.
Semiconductor Group
17
C511 / C513
Table 5 SFRs - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP SYSCON IE IP P0 P1 P2 P3 SSCCON STB SRB SCF SCIEN SSCMOD PCON SBUF SCON TCON TMOD TL0 TL1 TH0 TH1 T2CON T2MOD RC2L RC2H TL2 TH2
2) 2)
Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Stack Pointer System Control Reg. C511/C511A/C513 C513A/C513A-H Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register Power Control Register Serial Channel Buffer Register Serial Channel 1 Control Register Timer Control Register Timer Mode Register Timer 0, Low Byte Timer 1, Low Byte Timer 0, High Byte Timer 1, High Byte Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, Low Byte Timer 2 Reload/Capture Register, High Byte Timer 2 Low Byte Timer 2 High Byte Power Control Register
Address E0H 1) F0H 1) 83H 82H D0H 1) 81H B1H B1H A8H1) B8H 1) 80H 1) 90H 1) A0H 1) B0H 1) E8H 1) E9H EAH F8H 1) F9H EBH 87H 99H 98H 1) 88H 1) 89H 8AH 8BH 8CH 8DH C8H 1) C9H CAH CBH CCH CDH 87H
Contents after Reset 00H 00H 00H 00H 00H 07H 101X0XXXB 3) 101X0XX0B 3) 00H X0000000B 3) FFH FFH FFH FFH 07H XXH 3) XXH 3) XXXXXX00B 3) XXXXXX00B 3) 00H 0XXX0000B 3) XXH 3) 00H 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 3) 00H 00H 00H 00H 0XXX0000B 3)
Interrupt System Ports
SSC
USART
Timer 0 / Timer 1
Timer 2
Power PCON Save Mode
1) 2) 3)
Bit-addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks. X means that the value is indeterminate and the location is reserved
Semiconductor Group
18
C511 / C513
Table 6 Contents of the SFRs, SFRs in Numeric Order of their Addresses
Addr Register Content after Reset 1) FFH 07H 00H 00H 0XXX0000B 00H 00H 00H 00H 00H 00H FFH 00H XXH FFH 00H FFH
2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 90H 98H 99H A0H A8H B0H B1H B8H C8H C9H CAH CBH CCH CDH D0H E0H E8H E9H EAH EBH F0H
P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 P1 SCON SBUF P2 IE P3 SYSCON IP T2CON T2MOD RC2L RC2H TL2 TH2 PSW ACC SSCCON STB SRB SSCMOD B
.7 .7 .7 .7 SMOD TF1 GATE .7 .7 .7 .7 - SM0 .7 .7 EAL RD 1 - TF2 - .7 .7 .7 .7 CY .7 SCEN .7 .7
3)
.6 .6 .6 .6 - TR1 C/T .6 .6 .6 .6 - SM1 .6 .6 ESSC WR 0 PSSC EXF2 - .6 .6 .6 .6 AC .6 TEN .6 .6 0 .6
.5 .5 .5 .5 - TF0 M1 .5 .5 .5 .5 SLS SM2 .5 .5 ET2 T1 EALE PT2 RCLK - .5 .5 .5 .5 F0 .5 MSTR .5 .5 0 .5
.4 .4 .4 .4 - TR0 M0 .4 .4 .4 .4 STO REN .4 .4 ES0 T0 - PS TCLK - .4 .4 .4 .4 RS1 .4 CPOL .4 .4 0 .4
.3 .3 .3 .3 GF1 IE1 GATE .3 .3 .3 .3 SRI TB8 .3 .3 ET1 INT1 0 PT1 EXEN2 - .3 .3 .3 .3 RS0 .3 CPHA .3 .3 0 .3
.2 .2 .2 .2 GF0 IT1 C/T .2 .2 .2 .2 SCLK RB8 .2 .2 EX1 INT0 - PX1 TR2 - .2 .2 .2 .2 OV .2 BRS2 .2 .2 0 .2
.1 .1 .1 .1 PDE IE0 M1 .1 .1 .1 .1 T2EX TI .1 .1 ET0 TxD0 - PT0 C/T2 - .1 .1 .1 .1 F1 .1 BRS1 .1 .1 0 .1
.0 .0 .0 .0 IDLE IT0 M0 .0 .0 .0 .0 T2 RI .0 .0 EX0 RxD0 XMAP2) PX0 CP/ RL2 DCEN .0 .0 .0 .0 P .0 BRS0 .0 .0 0 .0
X0000000B 00H XXXXXXX0B 00H 00H 00H 00H 00H 00H 07H XXH XXH 00H 00H
0 .7
Semiconductor Group
19
C511 / C513
Table 6 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd)
Addr Register Content after Reset 1) XXXXXX00B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
F8H F9H
1) 2)
SCF SCIEN
-
-
-
-
-
-
WCOL
TC
3)
XXXX- - - - - - WCEN TCEN XX00B X means that the value is indeterminate and the location is reserved. The availability of the XMAP bit and the reset value of SYSCON depends on the specific microcontroller : C511/C511A/C513 : 101X0XXXB - bit XMAP is not available C513A/C513A-H : 101X0XX0B - bit XMAP is available This register ist only used for test purposes and must not be written. Otherwise unpredictable results may occur. Shaded registers are bit-addressable special function registers.
Semiconductor Group
20
C511 / C513
Timer/ Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 7: Table 7 Timer/Counter 0 and 1 operating modes Mode Description Gate 0 1 2 3 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit auto-reload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops X X X X TMOD C/T X X X X M1 0 0 1 1 M0 0 1 0 1 Input Clock internal external (max)
fOSC/12 x 32 fOSC/12 fOSC/12 fOSC/12
fOSC/24 x 32 fOSC/24 fOSC/24 fOSC/24
In "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the count rate is fOSC/12. In "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 7 illustrates the input clock logic.
Figure 7 Timer/Counter 0 and 1 Input Clock Logic Semiconductor Group 21
C511 / C513
Timer / Counter 2 (not available in the C511/C511A) Timer 2 is a 16-bit Timer/Counter with up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in table 8. Table 8 Timer/Counter 2 Operating Modes T2CON Mode RxCLK or TxCLK 0 0 0 0 16-bit Capture 0 CP/ RL2 0 0 0 0 1 TR2 1 1 1 1 1 T2MOD T2CON P1.1/ Remarks T2EX DCEN 0 0 1 1 X EXEN 0 1 X X 0 X 0 1 X reload upon overflow reload trigger (falling edge) Down counting Up counting 16-bit Timer/ Counter (only up-counting) capture TH2, TL2 RC2H, RC2L no overflow interrupt request (TF2) extra external interrupt ("Timer 2") Timer 2 stops Input Clock internal external (P1.0/T2)
16-bit Autoreload
fOSC/12
max
fOSC/24
0
1
1
X
1
fOSC/12
max
fOSC/24
Baud Rate Generator
1
X
1
X
0
X
1
X
1
X
1
fOSC/2
max fOSC/24
off Note: =
X
X
0
X
X
X
-
-
falling edge
Semiconductor Group
22
C511 / C513
Serial Interface (USART, not available in the C511/C511A) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 9. Figure 8 illustrates the block diagram of Baudrate generation for the serial interface. Table 9 USART Operating Modes Mode 0 SCON SM0 0 SM1 0 Baudrate Description Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bit are transmitted/received (LSB first) 8-bit UART 10 bits are transmitted (through TxD) or received (RxD) 9-bit UART 11 bits are transmitted (TxD) or received (RxD) 9-bit UART Like mode 2 except the variable baud rate
fOSC/12
1
0
1
Timer 1/2 overflow rate
2
1
0
fOSC/32 or fOSC/64
3
1
1
Timer 1/2 overflow rate
Figure 8 Block Diagram of Baud Rate Generation for the Serial Interface
Semiconductor Group
23
C511 / C513
The possible baudrates can be calculated using the formulas given in table 10. Table 10 Baudrates Selection Baud rate derived from Oscillator Timer 1 (16-bit timer) (8-bit timer with 8-bit autoreload) Timer 2 Interface Mode 0 2 1,3 1,3 1,3 Baudrate
fOSC/12 (2SMOD x fOSC)/64
(2SMOD x timer 1 overflow rate)/32 (2SMOD x fOSC)/(32 x 12 x (256-TH1))
fOSC/(32 x (65536-(RC2H, RC2L))
Semiconductor Group
24
C511 / C513
Synchronous Serial Channel (SSC) The C511/C513 microcontrollers provide a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. It can be used for simple I/O expansion via shift registers, for connection of a variety of peripheral components, such as A/D converters, EEPROMs etc., or for allowing several microcontrollers to be interconnected in a master/slave structure. It supports full-duplex or half-duplex operation and can run in a master or a slave mode. Figure 9 shows the block diagram of the SSC.
Figure 9 SSC Blockdiagram
Semiconductor Group
25
C511 / C513
Additional On-Chip XRAM (not available in the C511/C511A/C513) The C513A/C513A-H contain another 256 byte of on-chip RAM additional to the 256 byte internal RAM. This RAM is called XRAM (`eXtended RAM'). The additional on-chip XRAM is logically located in the external data memory range from address FF00H to FFFFH. The contents of the XRAM are not affected by a reset. After power up the content is undefined, while it remains unchanged during and after reset as long as the power supply is not turned off. The XRAM is controlled by SFR SYSCON as shown in table 11. Table 11 Control of the XRAM SFR SYSCON Bit XMAP 0 1 Description Reset value. Access to XRAM is disabled. XRAM enabled. The signals RD and WR are not activated during MOVX accesses in the XRAM address range.
The XRAM is accessed as external data memory. Therefore, MOVX instruction types must be used for accessing the XRAM. A general overview gives table 12. Table 12 Accessing the XRAM Instruction using DPTR (16-bit addr.) Instruction MOVX A @DPTR MOVX @DPTR,A Remarks Normally the use of these instructions would use a physically external memory. However, in the C513A/ C513A-H the XRAM is accessed if it is enabled by bit XMAP and the 16-bit address (DPTR) is within the XRAM address range FF00H - FFFFH. If XRAM is enabled in the C513A/C513A-H, MOVX instructions using Ri will always access the internal XRAM. External data memory cycles will not be generated in this case. If the XRAM is disabled, MOVX instructions using Ri will generate normal external data memory cycles.
R0/R1 (8-bit addr.)
MOVX A, @Ri MOVX @Ri,A
Semiconductor Group
26
C511 / C513
Interrupt System The C511/C513 provide 7 interrupt sources with two priority levels. Figure 10 gives a general overview of the interrupt sources and illustrates the request and control flags.
Figure 10 Interrupt Request Sources Semiconductor Group 27
C511 / C513
Table 13 Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 SSCI Vector External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt USART serial port interrupt, (C513/C513A/C513A-H only) Timer 2 interrupt Synchronous serial channel interrupt (SSC) Vector Address 0003H 000BH 0013H 001BH 0023H
002BH 0043H
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 14.
Table 14 Priority-within-Level Structure Interrupt Source External Interrupt 0, Synchronous Serial Channel Timer 0 Interrupt, External Interrupt 1, Timer 1 Interrupt, Universal Serial Channel, Timer 2 Interrupt, IE0 SSC TF0 IE1 TF1 RI or TI TF2 or EXF2 Priority High
Low
Semiconductor Group
28
C511 / C513
Power Saving Modes Two power down modes are available, the idle mode and the power down mode. In the idle mode only the CPU will be deactivated while in the power down mode the on-chip oscillator is stopped. The bits PDE and IDLE select the power down mode or the idle mode, respectively. If the power down mode and the idle mode are set at the same time, power down takes precedence. Table 15 gives a general overview of the power saving modes. Table 15 Entering and leaving the power saving modes Mode Idle mode Entering Example ORL PCON, #01H Leaving by - enabled interrupt - Hardware Reset Remarks CPU is gated off CPU status registers maintain their data. Peripherals are active Oscillators are stopped. Contents of on-chip RAM and SFR's are maintained (leaving power down mode means redefinition of SFR's contents)
Power Down Mode
ORL PCON, #02H
Hardware Reset
In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC is restored to its normal operating level, before the power down mode is terminated. The reset signal that terminates the power down mode also restarts the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset).
Semiconductor Group
29
C511 / C513
Absolute Maximum Ratings Ambient temperature under bias (TA) .............................................................. 0 C to + 70 C Storage temperature (TST) ...............................................................................- 65 C to + 150 C Voltage on VCC pins with respect to ground (VSS) ............................................- 0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS) ..............................................- 0.5 V to VCC + 0.5 V Input current on any pin during overload condition..........................................- 10 mA to + 10 mA Absolute sum of all input currents during overload condition ..........................| 100 mA | Power dissipation.............................................................................................TBD
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Semiconductor Group
30
C511 / C513
DC Characteristics VCC = 5 V + 10 %, - 15 %; VSS = 0 V; Parameter Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except EA, RESET, XTAL1) Input high voltage to XTAL1 Output low voltage Ports 1, 2, 3 (except P1.2, P1.4) Port 0, ALE, PSEN P1.2 / P1.4 pull-down transistor resistance Output high voltage Ports 1, 2, 3 Port 0 in ext. bus mode, ALE, PSEN P1.2 / P1.4 pull-up transistor resistance Logic 0 input current (Ports 1, 2, 3) Logical 1-to-0 transition current (Ports 1, 2, 3) Maximum output low current per pin (Ports 0, 1, 2, 3) Maximum output low current per port Input leakage current Port 0 (if EA=0), EA, P1.2, P1.3, P1.5 as SSC inputs Pin capacitance
7)
TA = 0 to + 70 C
Limit Values min. max. 0.2 VCC - 0.1 0.2 VCC - 0.3 0.2 VCC + 0.1 V V V V V V V - - - - - - - 0.5 - 0.5 - 0.5 0.2 VCC + 0.9 0.7 VCC 0.6 VCC - - - Unit Test Condition
Symbol
VIL VIL1 VIL2 VIH VIH1
VCC + 0.5 VCC + 0.5 VCC + 0.5
0.45 0.45 120
Input high voltage to EA, RESET VIH2
VOL VOL1 RDSon
V
IOL = 1.6 mA 1) IOL = 3.2 mA 1) VOL = 0.45 V
VOH VOH1 RDSon IIL ITL IOLM IPL
2.4 0.9 VCC 2.4 0.9 VCC - - 10 - 65 - -
- - - - 120 - 50 - 650 5 30
V V V V A A mA mA
IOH = - 80 A IOH = - 10 A IOH = - 800 A IOH = - 80 A VOH = 0.9 VCC VIN = 0.45 V VIN = 2 V VOL 1 V
-
ILI CIO
- -
1 10
A pF
0.45 < VIN < VCC
fC = 1 MHz, TA = 25 C
Semiconductor Group
31
C511 / C513
DC Characteristics (cont'd) VCC = 5 V + 10 %, - 15 %; VSS = 0 V; Parameter Power supply current: C511/C511A/C513/C513A Active mode, 12 MHz 6) Idle mode, 12 MHz 6) Power Down Mode C513A-H Active mode, 12 MHz 6) Idle mode, 12 MHz 6) Power Down Mode Notes:
1)
TA = 0 to + 70 C
Limit Values typ. 8) max. Unit Test Condition
Symbol
ICC ICC IPD ICC ICC IPD
7 3.5 TBD 16 6 TBD
9.5 4.5 50 TBD TBD 50
mA mA A mA mA A
VCC = 5 V,4) VCC = 5 V,5) VCC = 2 ... 5.5 V,3) VCC = 5 V,4) VCC = 5 V,5) VCC = 2 ... 5.5 V3)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall bellow the 0.9 VCC specification when the address lines are stabilizing.
2)
3)
IPD (Power Down Mode) is measured under following conditions: EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VCC; all other pins are disconnected. ICC (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 = N.C.; EA = Port0 = RESET = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator
is used (appr. 1 mA).
4)
5)
ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VCC; all other pins are disconnected; ICC Max at other frequencies is given by: C511/C511A/C513/C513A : Active mode: TBD Idle mode: TBD C513A-H : Active mode: TBD Idle mode: TBD where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5 V.
This parameter is periodically sampled and not 100% tested. The typical ICC values are periodically measured at TA = +25 C but not 100% tested.
6)
7)
8)
Semiconductor Group
32
C511 / C513
AC Characteristics (applies to all C511/513 Family Microcontrollers)
VCC = 5 V + 10 %, - 15 %; VSS = 0 V
TA = 0 C to + 70 C
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 12 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to PSEN PSEN pulse width PSEN to valid instr in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN max. - - - 233 - - 150 - 63 - 302 - Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. 2tCLCL - 40 max. - - - 4tCLCL - 100 - - 3tCLCL - 100 - ns ns ns ns ns ns ns ns ns ns ns ns Unit
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL
127 43 60 - 58 215 - 0 - 75 - 0
tCLCL - 40 tCLCL - 23
-
tCLCL - 25
3tCLCL - 35 - 0 -
tCLCL - 20
- 5tCLCL - 115 -
tCLCL - 8
- 0
*) Interfacing the C511/513 microcontrollers to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
Semiconductor Group
33
C511 / C513
External Data Memory Characteristics Parameter Symbol 12 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 252 - 97 517 585 300 - 123 - - - 0 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. 6tCLCL - 100 6tCLCL - 100 max. - - - 5tCLCL - 165 - 2tCLCL - 70 8tCLCL - 150 9tCLCL - 165 3tCLCL + 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ
400 400 132 - 0 - - - 200 203 43 33 433 33 -
2tCLCL - 35
- 0 - - - 3tCLCL - 50 4tCLCL - 130
tCLCL - 40 tCLCL - 50
7tCLCL - 150
tCLCL + 40
- - - 0
tCLCL - 50
-
Semiconductor Group
34
C511 / C513
SSC Interface Characteristics Parameter Symbol min. Clock Cycle Time : Master Mode Slave Mode Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay Limit Values 12 MHz Clock max. - - - - 100 - - - 16 tCLCL ns ns ns ns ns ns ns ns ns Unit
tSCLK tSCLK tSCH tSCL tD tHO tS tHI tDTC
666 600 250 250 - 0 100 100 -
External Clock Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 12 MHz min. Oscillator period High time Low time Rise time Fall time max. 285 ns ns ns ns ns Unit
tCLCL tCHCX tCLCX tCLCH tCHCL
83.3 20 20 - -
tCLCL - tCLCX tCLCL - tCHCX
20 20
Semiconductor Group
35
C511 / C513
Figure 11 Program Memory Read Cycle
Figure 12 Data Memory Read Cycle Semiconductor Group 36
C511 / C513
Figure 13 Data Memory Write Cycle
Semiconductor Group
37
C511 / C513
Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA = 0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition. Figure 14 SSC Timing
Figure 15 External Clock Drive at XTAL1
Semiconductor Group
38
C511 / C513
ROM Verification Characteristics (only ROM versions C511 / C511A / C513 / C513A) Parameter Address to valid data ENABLE to valid data Data float after ENABLE Oscillator frequency Symbol min. Limit Values max. 48tCLCL 48tCLCL 48tCLCL 6 ns ns ns MHz - - 0 4 Unit
tAVQV tELQV tEHQZ
1/tCLCL
Device Type ROM Size C511 C511A C513 C513A 2.5 KB 4 KB 8 KB 12/16 KB
Active Address Lines at Port 2 P2.0 - P2.3 = A8 - A11 P2.0 - P2.3 = A8 - A11 P2.0 - P2.4 = A8 - A12 P2.0 - P2.5 = A8 - A13
Inactive Address Lines at Port 2 P2.4 - P2.6 = VSS P2.4 - P2.6 = VSS P2.5 - P2.6 = VSS P2.6 = VSS
Figure 16 ROM Verification Timing
Semiconductor Group
39
C511 / C513
AC Characteristics of C513A-H Programming Interface
VCC = 5 V 10 %, VSS = 0 V; TA = +25 C 10 C; 1/tCLCL = 8 MHz
Parameter ALE pulse width Address setup to ALE Address hold after ALE Address to valid data out PRD/PWR pulse width PRD to valid data out Data hold after PWR Data float after PRD Chip select setup to ALE active Chip select hold after PRD/PWR inactive ALE to PWR or PRD PWR or PRD high to ALE high Data setup before PWR rising edge Data hold after PWR rising edge Data float after PCS Symbol min. Limit Values max. - - - 230 - 200 - 40 - - - - - - 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 60 20 20 - 250 - 0 - 0 0 90 20 50 0 - Unit
tPLL tPAL tPLA tPAD tPCC tPRDV tPWDH tPDZ tPCS tPCH tPLC tPCL tPWDS tPWDH tPDF
Semiconductor Group
40
C511 / C513
Figure 17 C513A-H Programming Interface Read Cycle
Figure 18 C513A-H Programming Interface Write Cycle
Semiconductor Group
41
C511 / C513
Reset Characteristics (C513A-H only) Parameter Symbol 12 MHz Clock min. RESET pulse width max. - Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 12 MHz min. 10 max. - ms Unit
tRLRH
10
Figure 19 C513A-H Reset Pulse
Semiconductor Group
42
C511 / C513
AC Inputs during testing are driven at VCC - 0.5 V for a logic '1' and 0.45 V for a logic '0'. Timing measurements are made at VIHmin for a logic '1' and VILmax for a logic '0'. Figure 20 AC Testing: Input, Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA Figure 21 AC Testing: Float Waveforms
Figure 22 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 43

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